The present invention relates to an arithmetic operation circuit for finding a square root of a sum of squared values.
For finding an absolute value of a vector, a function of .sqroot.X1.sup.2 +X2.sup.2 is calculated. In the case of a two dimensional vector, two vector components X1 and X2 are each squared and then a square root of their sum is calculated. A bipolar IC for executing such an operation is disclosed in "Root-law Circuit Using Monolithic Bipolar-transistor Arrays", Electronics letters Oct. 17, 1974, Vol. 10, No. 21, pp. 439-440, by R. W. J. Barker and B. L. Hart and in "Transistor Circuits: A Proposed Classification", Electronics Letters, Mar. 20, 1975, Vol. 11, No. 6, pp. 136, by B. Gilbert.
An arithmetic operation circuit for finding a square root of a sum of squared values according to the present invention is based on an idea different from those prior art concepts.